using glide

vendor/github.com/klauspost/cpuid/private/README.md

@@ -0,0 +1,6 @@
+# cpuid private
+
+This is a specially converted of the cpuid package, so it can be included in
+a package without exporting anything.
+
+Package home: https://github.com/klauspost/cpuid

vendor/github.com/klauspost/cpuid/private/cpuid.go

@@ -0,0 +1,987 @@
+// Generated, DO NOT EDIT,
+// but copy it to your own project and rename the package.
+// See more at http://github.com/klauspost/cpuid
+
+package cpuid
+
+import (
+	"strings"
+)
+
+// Vendor is a representation of a CPU vendor.
+type vendor int
+
+const (
+	other	vendor	= iota
+	intel
+	amd
+	via
+	transmeta
+	nsc
+	kvm	// Kernel-based Virtual Machine
+	msvm	// Microsoft Hyper-V or Windows Virtual PC
+	vmware
+	xenhvm
+)
+
+const (
+	cmov		= 1 << iota	// i686 CMOV
+	nx				// NX (No-Execute) bit
+	amd3dnow			// AMD 3DNOW
+	amd3dnowext			// AMD 3DNowExt
+	mmx				// standard MMX
+	mmxext				// SSE integer functions or AMD MMX ext
+	sse				// SSE functions
+	sse2				// P4 SSE functions
+	sse3				// Prescott SSE3 functions
+	ssse3				// Conroe SSSE3 functions
+	sse4				// Penryn SSE4.1 functions
+	sse4a				// AMD Barcelona microarchitecture SSE4a instructions
+	sse42				// Nehalem SSE4.2 functions
+	avx				// AVX functions
+	avx2				// AVX2 functions
+	fma3				// Intel FMA 3
+	fma4				// Bulldozer FMA4 functions
+	xop				// Bulldozer XOP functions
+	f16c				// Half-precision floating-point conversion
+	bmi1				// Bit Manipulation Instruction Set 1
+	bmi2				// Bit Manipulation Instruction Set 2
+	tbm				// AMD Trailing Bit Manipulation
+	lzcnt				// LZCNT instruction
+	popcnt				// POPCNT instruction
+	aesni				// Advanced Encryption Standard New Instructions
+	clmul				// Carry-less Multiplication
+	htt				// Hyperthreading (enabled)
+	hle				// Hardware Lock Elision
+	rtm				// Restricted Transactional Memory
+	rdrand				// RDRAND instruction is available
+	rdseed				// RDSEED instruction is available
+	adx				// Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
+	sha				// Intel SHA Extensions
+	avx512f				// AVX-512 Foundation
+	avx512dq			// AVX-512 Doubleword and Quadword Instructions
+	avx512ifma			// AVX-512 Integer Fused Multiply-Add Instructions
+	avx512pf			// AVX-512 Prefetch Instructions
+	avx512er			// AVX-512 Exponential and Reciprocal Instructions
+	avx512cd			// AVX-512 Conflict Detection Instructions
+	avx512bw			// AVX-512 Byte and Word Instructions
+	avx512vl			// AVX-512 Vector Length Extensions
+	avx512vbmi			// AVX-512 Vector Bit Manipulation Instructions
+	mpx				// Intel MPX (Memory Protection Extensions)
+	erms				// Enhanced REP MOVSB/STOSB
+	rdtscp				// RDTSCP Instruction
+	cx16				// CMPXCHG16B Instruction
+
+	// Performance indicators
+	sse2slow	// SSE2 is supported, but usually not faster
+	sse3slow	// SSE3 is supported, but usually not faster
+	atom		// Atom processor, some SSSE3 instructions are slower
+)
+
+var flagNames = map[flags]string{
+	cmov:		"CMOV",		// i686 CMOV
+	nx:		"NX",		// NX (No-Execute) bit
+	amd3dnow:	"AMD3DNOW",	// AMD 3DNOW
+	amd3dnowext:	"AMD3DNOWEXT",	// AMD 3DNowExt
+	mmx:		"MMX",		// Standard MMX
+	mmxext:		"MMXEXT",	// SSE integer functions or AMD MMX ext
+	sse:		"SSE",		// SSE functions
+	sse2:		"SSE2",		// P4 SSE2 functions
+	sse3:		"SSE3",		// Prescott SSE3 functions
+	ssse3:		"SSSE3",	// Conroe SSSE3 functions
+	sse4:		"SSE4.1",	// Penryn SSE4.1 functions
+	sse4a:		"SSE4A",	// AMD Barcelona microarchitecture SSE4a instructions
+	sse42:		"SSE4.2",	// Nehalem SSE4.2 functions
+	avx:		"AVX",		// AVX functions
+	avx2:		"AVX2",		// AVX functions
+	fma3:		"FMA3",		// Intel FMA 3
+	fma4:		"FMA4",		// Bulldozer FMA4 functions
+	xop:		"XOP",		// Bulldozer XOP functions
+	f16c:		"F16C",		// Half-precision floating-point conversion
+	bmi1:		"BMI1",		// Bit Manipulation Instruction Set 1
+	bmi2:		"BMI2",		// Bit Manipulation Instruction Set 2
+	tbm:		"TBM",		// AMD Trailing Bit Manipulation
+	lzcnt:		"LZCNT",	// LZCNT instruction
+	popcnt:		"POPCNT",	// POPCNT instruction
+	aesni:		"AESNI",	// Advanced Encryption Standard New Instructions
+	clmul:		"CLMUL",	// Carry-less Multiplication
+	htt:		"HTT",		// Hyperthreading (enabled)
+	hle:		"HLE",		// Hardware Lock Elision
+	rtm:		"RTM",		// Restricted Transactional Memory
+	rdrand:		"RDRAND",	// RDRAND instruction is available
+	rdseed:		"RDSEED",	// RDSEED instruction is available
+	adx:		"ADX",		// Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
+	sha:		"SHA",		// Intel SHA Extensions
+	avx512f:	"AVX512F",	// AVX-512 Foundation
+	avx512dq:	"AVX512DQ",	// AVX-512 Doubleword and Quadword Instructions
+	avx512ifma:	"AVX512IFMA",	// AVX-512 Integer Fused Multiply-Add Instructions
+	avx512pf:	"AVX512PF",	// AVX-512 Prefetch Instructions
+	avx512er:	"AVX512ER",	// AVX-512 Exponential and Reciprocal Instructions
+	avx512cd:	"AVX512CD",	// AVX-512 Conflict Detection Instructions
+	avx512bw:	"AVX512BW",	// AVX-512 Byte and Word Instructions
+	avx512vl:	"AVX512VL",	// AVX-512 Vector Length Extensions
+	avx512vbmi:	"AVX512VBMI",	// AVX-512 Vector Bit Manipulation Instructions
+	mpx:		"MPX",		// Intel MPX (Memory Protection Extensions)
+	erms:		"ERMS",		// Enhanced REP MOVSB/STOSB
+	rdtscp:		"RDTSCP",	// RDTSCP Instruction
+	cx16:		"CX16",		// CMPXCHG16B Instruction
+
+	// Performance indicators
+	sse2slow:	"SSE2SLOW",	// SSE2 supported, but usually not faster
+	sse3slow:	"SSE3SLOW",	// SSE3 supported, but usually not faster
+	atom:		"ATOM",		// Atom processor, some SSSE3 instructions are slower
+
+}
+
+// CPUInfo contains information about the detected system CPU.
+type cpuInfo struct {
+	brandname	string	// Brand name reported by the CPU
+	vendorid	vendor	// Comparable CPU vendor ID
+	features	flags	// Features of the CPU
+	physicalcores	int	// Number of physical processor cores in your CPU. Will be 0 if undetectable.
+	threadspercore	int	// Number of threads per physical core. Will be 1 if undetectable.
+	logicalcores	int	// Number of physical cores times threads that can run on each core through the use of hyperthreading. Will be 0 if undetectable.
+	family		int	// CPU family number
+	model		int	// CPU model number
+	cacheline	int	// Cache line size in bytes. Will be 0 if undetectable.
+	cache		struct {
+		l1i	int	// L1 Instruction Cache (per core or shared). Will be -1 if undetected
+		l1d	int	// L1 Data Cache (per core or shared). Will be -1 if undetected
+		l2	int	// L2 Cache (per core or shared). Will be -1 if undetected
+		l3	int	// L3 Instruction Cache (per core or shared). Will be -1 if undetected
+	}
+	maxFunc		uint32
+	maxExFunc	uint32
+}
+
+var cpuid func(op uint32) (eax, ebx, ecx, edx uint32)
+var cpuidex func(op, op2 uint32) (eax, ebx, ecx, edx uint32)
+var xgetbv func(index uint32) (eax, edx uint32)
+var rdtscpAsm func() (eax, ebx, ecx, edx uint32)
+
+// CPU contains information about the CPU as detected on startup,
+// or when Detect last was called.
+//
+// Use this as the primary entry point to you data,
+// this way queries are
+var cpu cpuInfo
+
+func init() {
+	initCPU()
+	detect()
+}
+
+// Detect will re-detect current CPU info.
+// This will replace the content of the exported CPU variable.
+//
+// Unless you expect the CPU to change while you are running your program
+// you should not need to call this function.
+// If you call this, you must ensure that no other goroutine is accessing the
+// exported CPU variable.
+func detect() {
+	cpu.maxFunc = maxFunctionID()
+	cpu.maxExFunc = maxExtendedFunction()
+	cpu.brandname = brandName()
+	cpu.cacheline = cacheLine()
+	cpu.family, cpu.model = familyModel()
+	cpu.features = support()
+	cpu.threadspercore = threadsPerCore()
+	cpu.logicalcores = logicalCores()
+	cpu.physicalcores = physicalCores()
+	cpu.vendorid = vendorID()
+	cpu.cacheSize()
+}
+
+// Generated here: http://play.golang.org/p/BxFH2Gdc0G
+
+// Cmov indicates support of CMOV instructions
+func (c cpuInfo) cmov() bool {
+	return c.features&cmov != 0
+}
+
+// Amd3dnow indicates support of AMD 3DNOW! instructions
+func (c cpuInfo) amd3dnow() bool {
+	return c.features&amd3dnow != 0
+}
+
+// Amd3dnowExt indicates support of AMD 3DNOW! Extended instructions
+func (c cpuInfo) amd3dnowext() bool {
+	return c.features&amd3dnowext != 0
+}
+
+// MMX indicates support of MMX instructions
+func (c cpuInfo) mmx() bool {
+	return c.features&mmx != 0
+}
+
+// MMXExt indicates support of MMXEXT instructions
+// (SSE integer functions or AMD MMX ext)
+func (c cpuInfo) mmxext() bool {
+	return c.features&mmxext != 0
+}
+
+// SSE indicates support of SSE instructions
+func (c cpuInfo) sse() bool {
+	return c.features&sse != 0
+}
+
+// SSE2 indicates support of SSE 2 instructions
+func (c cpuInfo) sse2() bool {
+	return c.features&sse2 != 0
+}
+
+// SSE3 indicates support of SSE 3 instructions
+func (c cpuInfo) sse3() bool {
+	return c.features&sse3 != 0
+}
+
+// SSSE3 indicates support of SSSE 3 instructions
+func (c cpuInfo) ssse3() bool {
+	return c.features&ssse3 != 0
+}
+
+// SSE4 indicates support of SSE 4 (also called SSE 4.1) instructions
+func (c cpuInfo) sse4() bool {
+	return c.features&sse4 != 0
+}
+
+// SSE42 indicates support of SSE4.2 instructions
+func (c cpuInfo) sse42() bool {
+	return c.features&sse42 != 0
+}
+
+// AVX indicates support of AVX instructions
+// and operating system support of AVX instructions
+func (c cpuInfo) avx() bool {
+	return c.features&avx != 0
+}
+
+// AVX2 indicates support of AVX2 instructions
+func (c cpuInfo) avx2() bool {
+	return c.features&avx2 != 0
+}
+
+// FMA3 indicates support of FMA3 instructions
+func (c cpuInfo) fma3() bool {
+	return c.features&fma3 != 0
+}
+
+// FMA4 indicates support of FMA4 instructions
+func (c cpuInfo) fma4() bool {
+	return c.features&fma4 != 0
+}
+
+// XOP indicates support of XOP instructions
+func (c cpuInfo) xop() bool {
+	return c.features&xop != 0
+}
+
+// F16C indicates support of F16C instructions
+func (c cpuInfo) f16c() bool {
+	return c.features&f16c != 0
+}
+
+// BMI1 indicates support of BMI1 instructions
+func (c cpuInfo) bmi1() bool {
+	return c.features&bmi1 != 0
+}
+
+// BMI2 indicates support of BMI2 instructions
+func (c cpuInfo) bmi2() bool {
+	return c.features&bmi2 != 0
+}
+
+// TBM indicates support of TBM instructions
+// (AMD Trailing Bit Manipulation)
+func (c cpuInfo) tbm() bool {
+	return c.features&tbm != 0
+}
+
+// Lzcnt indicates support of LZCNT instruction
+func (c cpuInfo) lzcnt() bool {
+	return c.features&lzcnt != 0
+}
+
+// Popcnt indicates support of POPCNT instruction
+func (c cpuInfo) popcnt() bool {
+	return c.features&popcnt != 0
+}
+
+// HTT indicates the processor has Hyperthreading enabled
+func (c cpuInfo) htt() bool {
+	return c.features&htt != 0
+}
+
+// SSE2Slow indicates that SSE2 may be slow on this processor
+func (c cpuInfo) sse2slow() bool {
+	return c.features&sse2slow != 0
+}
+
+// SSE3Slow indicates that SSE3 may be slow on this processor
+func (c cpuInfo) sse3slow() bool {
+	return c.features&sse3slow != 0
+}
+
+// AesNi indicates support of AES-NI instructions
+// (Advanced Encryption Standard New Instructions)
+func (c cpuInfo) aesni() bool {
+	return c.features&aesni != 0
+}
+
+// Clmul indicates support of CLMUL instructions
+// (Carry-less Multiplication)
+func (c cpuInfo) clmul() bool {
+	return c.features&clmul != 0
+}
+
+// NX indicates support of NX (No-Execute) bit
+func (c cpuInfo) nx() bool {
+	return c.features&nx != 0
+}
+
+// SSE4A indicates support of AMD Barcelona microarchitecture SSE4a instructions
+func (c cpuInfo) sse4a() bool {
+	return c.features&sse4a != 0
+}
+
+// HLE indicates support of Hardware Lock Elision
+func (c cpuInfo) hle() bool {
+	return c.features&hle != 0
+}
+
+// RTM indicates support of Restricted Transactional Memory
+func (c cpuInfo) rtm() bool {
+	return c.features&rtm != 0
+}
+
+// Rdrand indicates support of RDRAND instruction is available
+func (c cpuInfo) rdrand() bool {
+	return c.features&rdrand != 0
+}
+
+// Rdseed indicates support of RDSEED instruction is available
+func (c cpuInfo) rdseed() bool {
+	return c.features&rdseed != 0
+}
+
+// ADX indicates support of Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
+func (c cpuInfo) adx() bool {
+	return c.features&adx != 0
+}
+
+// SHA indicates support of Intel SHA Extensions
+func (c cpuInfo) sha() bool {
+	return c.features&sha != 0
+}
+
+// AVX512F indicates support of AVX-512 Foundation
+func (c cpuInfo) avx512f() bool {
+	return c.features&avx512f != 0
+}
+
+// AVX512DQ indicates support of AVX-512 Doubleword and Quadword Instructions
+func (c cpuInfo) avx512dq() bool {
+	return c.features&avx512dq != 0
+}
+
+// AVX512IFMA indicates support of AVX-512 Integer Fused Multiply-Add Instructions
+func (c cpuInfo) avx512ifma() bool {
+	return c.features&avx512ifma != 0
+}
+
+// AVX512PF indicates support of AVX-512 Prefetch Instructions
+func (c cpuInfo) avx512pf() bool {
+	return c.features&avx512pf != 0
+}
+
+// AVX512ER indicates support of AVX-512 Exponential and Reciprocal Instructions
+func (c cpuInfo) avx512er() bool {
+	return c.features&avx512er != 0
+}
+
+// AVX512CD indicates support of AVX-512 Conflict Detection Instructions
+func (c cpuInfo) avx512cd() bool {
+	return c.features&avx512cd != 0
+}
+
+// AVX512BW indicates support of AVX-512 Byte and Word Instructions
+func (c cpuInfo) avx512bw() bool {
+	return c.features&avx512bw != 0
+}
+
+// AVX512VL indicates support of AVX-512 Vector Length Extensions
+func (c cpuInfo) avx512vl() bool {
+	return c.features&avx512vl != 0
+}
+
+// AVX512VBMI indicates support of AVX-512 Vector Bit Manipulation Instructions
+func (c cpuInfo) avx512vbmi() bool {
+	return c.features&avx512vbmi != 0
+}
+
+// MPX indicates support of Intel MPX (Memory Protection Extensions)
+func (c cpuInfo) mpx() bool {
+	return c.features&mpx != 0
+}
+
+// ERMS indicates support of Enhanced REP MOVSB/STOSB
+func (c cpuInfo) erms() bool {
+	return c.features&erms != 0
+}
+
+func (c cpuInfo) rdtscp() bool {
+	return c.features&rdtscp != 0
+}
+
+func (c cpuInfo) cx16() bool {
+	return c.features&cx16 != 0
+}
+
+// Atom indicates an Atom processor
+func (c cpuInfo) atom() bool {
+	return c.features&atom != 0
+}
+
+// Intel returns true if vendor is recognized as Intel
+func (c cpuInfo) intel() bool {
+	return c.vendorid == intel
+}
+
+// AMD returns true if vendor is recognized as AMD
+func (c cpuInfo) amd() bool {
+	return c.vendorid == amd
+}
+
+// Transmeta returns true if vendor is recognized as Transmeta
+func (c cpuInfo) transmeta() bool {
+	return c.vendorid == transmeta
+}
+
+// NSC returns true if vendor is recognized as National Semiconductor
+func (c cpuInfo) nsc() bool {
+	return c.vendorid == nsc
+}
+
+// VIA returns true if vendor is recognized as VIA
+func (c cpuInfo) via() bool {
+	return c.vendorid == via
+}
+
+// RTCounter returns the 64-bit time-stamp counter
+// Uses the RDTSCP instruction. The value 0 is returned
+// if the CPU does not support the instruction.
+func (c cpuInfo) rtcounter() uint64 {
+	if !c.rdtscp() {
+		return 0
+	}
+	a, _, _, d := rdtscpAsm()
+	return uint64(a) | (uint64(d) << 32)
+}
+
+// Ia32TscAux returns the IA32_TSC_AUX part of the RDTSCP.
+// This variable is OS dependent, but on Linux contains information
+// about the current cpu/core the code is running on.
+// If the RDTSCP instruction isn't supported on the CPU, the value 0 is returned.
+func (c cpuInfo) ia32tscaux() uint32 {
+	if !c.rdtscp() {
+		return 0
+	}
+	_, _, ecx, _ := rdtscpAsm()
+	return ecx
+}
+
+// LogicalCPU will return the Logical CPU the code is currently executing on.
+// This is likely to change when the OS re-schedules the running thread
+// to another CPU.
+// If the current core cannot be detected, -1 will be returned.
+func (c cpuInfo) logicalcpu() int {
+	if c.maxFunc < 1 {
+		return -1
+	}
+	_, ebx, _, _ := cpuid(1)
+	return int(ebx >> 24)
+}
+
+// VM Will return true if the cpu id indicates we are in
+// a virtual machine. This is only a hint, and will very likely
+// have many false negatives.
+func (c cpuInfo) vm() bool {
+	switch c.vendorid {
+	case msvm, kvm, vmware, xenhvm:
+		return true
+	}
+	return false
+}
+
+// Flags contains detected cpu features and caracteristics
+type flags uint64
+
+// String returns a string representation of the detected
+// CPU features.
+func (f flags) String() string {
+	return strings.Join(f.strings(), ",")
+}
+
+// Strings returns and array of the detected features.
+func (f flags) strings() []string {
+	s := support()
+	r := make([]string, 0, 20)
+	for i := uint(0); i < 64; i++ {
+		key := flags(1 << i)
+		val := flagNames[key]
+		if s&key != 0 {
+			r = append(r, val)
+		}
+	}
+	return r
+}
+
+func maxExtendedFunction() uint32 {
+	eax, _, _, _ := cpuid(0x80000000)
+	return eax
+}
+
+func maxFunctionID() uint32 {
+	a, _, _, _ := cpuid(0)
+	return a
+}
+
+func brandName() string {
+	if maxExtendedFunction() >= 0x80000004 {
+		v := make([]uint32, 0, 48)
+		for i := uint32(0); i < 3; i++ {
+			a, b, c, d := cpuid(0x80000002 + i)
+			v = append(v, a, b, c, d)
+		}
+		return strings.Trim(string(valAsString(v...)), " ")
+	}
+	return "unknown"
+}
+
+func threadsPerCore() int {
+	mfi := maxFunctionID()
+	if mfi < 0x4 || vendorID() != intel {
+		return 1
+	}
+
+	if mfi < 0xb {
+		_, b, _, d := cpuid(1)
+		if (d & (1 << 28)) != 0 {
+			// v will contain logical core count
+			v := (b >> 16) & 255
+			if v > 1 {
+				a4, _, _, _ := cpuid(4)
+				// physical cores
+				v2 := (a4 >> 26) + 1
+				if v2 > 0 {
+					return int(v) / int(v2)
+				}
+			}
+		}
+		return 1
+	}
+	_, b, _, _ := cpuidex(0xb, 0)
+	if b&0xffff == 0 {
+		return 1
+	}
+	return int(b & 0xffff)
+}
+
+func logicalCores() int {
+	mfi := maxFunctionID()
+	switch vendorID() {
+	case intel:
+		// Use this on old Intel processors
+		if mfi < 0xb {
+			if mfi < 1 {
+				return 0
+			}
+			// CPUID.1:EBX[23:16] represents the maximum number of addressable IDs (initial APIC ID)
+			// that can be assigned to logical processors in a physical package.
+			// The value may not be the same as the number of logical processors that are present in the hardware of a physical package.
+			_, ebx, _, _ := cpuid(1)
+			logical := (ebx >> 16) & 0xff
+			return int(logical)
+		}
+		_, b, _, _ := cpuidex(0xb, 1)
+		return int(b & 0xffff)
+	case amd:
+		_, b, _, _ := cpuid(1)
+		return int((b >> 16) & 0xff)
+	default:
+		return 0
+	}
+}
+
+func familyModel() (int, int) {
+	if maxFunctionID() < 0x1 {
+		return 0, 0
+	}
+	eax, _, _, _ := cpuid(1)
+	family := ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff)
+	model := ((eax >> 4) & 0xf) + ((eax >> 12) & 0xf0)
+	return int(family), int(model)
+}
+
+func physicalCores() int {
+	switch vendorID() {
+	case intel:
+		return logicalCores() / threadsPerCore()
+	case amd:
+		if maxExtendedFunction() >= 0x80000008 {
+			_, _, c, _ := cpuid(0x80000008)
+			return int(c&0xff) + 1
+		}
+	}
+	return 0
+}
+
+// Except from http://en.wikipedia.org/wiki/CPUID#EAX.3D0:_Get_vendor_ID
+var vendorMapping = map[string]vendor{
+	"AMDisbetter!":	amd,
+	"AuthenticAMD":	amd,
+	"CentaurHauls":	via,
+	"GenuineIntel":	intel,
+	"TransmetaCPU":	transmeta,
+	"GenuineTMx86":	transmeta,
+	"Geode by NSC":	nsc,
+	"VIA VIA VIA ":	via,
+	"KVMKVMKVMKVM":	kvm,
+	"Microsoft Hv":	msvm,
+	"VMwareVMware":	vmware,
+	"XenVMMXenVMM":	xenhvm,
+}
+
+func vendorID() vendor {
+	_, b, c, d := cpuid(0)
+	v := valAsString(b, d, c)
+	vend, ok := vendorMapping[string(v)]
+	if !ok {
+		return other
+	}
+	return vend
+}
+
+func cacheLine() int {
+	if maxFunctionID() < 0x1 {
+		return 0
+	}
+
+	_, ebx, _, _ := cpuid(1)
+	cache := (ebx & 0xff00) >> 5	// cflush size
+	if cache == 0 && maxExtendedFunction() >= 0x80000006 {
+		_, _, ecx, _ := cpuid(0x80000006)
+		cache = ecx & 0xff	// cacheline size
+	}
+	// TODO: Read from Cache and TLB Information
+	return int(cache)
+}
+
+func (c *cpuInfo) cacheSize() {
+	c.cache.l1d = -1
+	c.cache.l1i = -1
+	c.cache.l2 = -1
+	c.cache.l3 = -1
+	vendor := vendorID()
+	switch vendor {
+	case intel:
+		if maxFunctionID() < 4 {
+			return
+		}
+		for i := uint32(0); ; i++ {
+			eax, ebx, ecx, _ := cpuidex(4, i)
+			cacheType := eax & 15
+			if cacheType == 0 {
+				break
+			}
+			cacheLevel := (eax >> 5) & 7
+			coherency := int(ebx&0xfff) + 1
+			partitions := int((ebx>>12)&0x3ff) + 1
+			associativity := int((ebx>>22)&0x3ff) + 1
+			sets := int(ecx) + 1
+			size := associativity * partitions * coherency * sets
+			switch cacheLevel {
+			case 1:
+				if cacheType == 1 {
+					// 1 = Data Cache
+					c.cache.l1d = size
+				} else if cacheType == 2 {
+					// 2 = Instruction Cache
+					c.cache.l1i = size
+				} else {
+					if c.cache.l1d < 0 {
+						c.cache.l1i = size
+					}
+					if c.cache.l1i < 0 {
+						c.cache.l1i = size
+					}
+				}
+			case 2:
+				c.cache.l2 = size
+			case 3:
+				c.cache.l3 = size
+			}
+		}
+	case amd:
+		// Untested.
+		if maxExtendedFunction() < 0x80000005 {
+			return
+		}
+		_, _, ecx, edx := cpuid(0x80000005)
+		c.cache.l1d = int(((ecx >> 24) & 0xFF) * 1024)
+		c.cache.l1i = int(((edx >> 24) & 0xFF) * 1024)
+
+		if maxExtendedFunction() < 0x80000006 {
+			return
+		}
+		_, _, ecx, _ = cpuid(0x80000006)
+		c.cache.l2 = int(((ecx >> 16) & 0xFFFF) * 1024)
+	}
+
+	return
+}
+
+func support() flags {
+	mfi := maxFunctionID()
+	vend := vendorID()
+	if mfi < 0x1 {
+		return 0
+	}
+	rval := uint64(0)
+	_, _, c, d := cpuid(1)
+	if (d & (1 << 15)) != 0 {
+		rval |= cmov
+	}
+	if (d & (1 << 23)) != 0 {
+		rval |= mmx
+	}
+	if (d & (1 << 25)) != 0 {
+		rval |= mmxext
+	}
+	if (d & (1 << 25)) != 0 {
+		rval |= sse
+	}
+	if (d & (1 << 26)) != 0 {
+		rval |= sse2
+	}
+	if (c & 1) != 0 {
+		rval |= sse3
+	}
+	if (c & 0x00000200) != 0 {
+		rval |= ssse3
+	}
+	if (c & 0x00080000) != 0 {
+		rval |= sse4
+	}
+	if (c & 0x00100000) != 0 {
+		rval |= sse42
+	}
+	if (c & (1 << 25)) != 0 {
+		rval |= aesni
+	}
+	if (c & (1 << 1)) != 0 {
+		rval |= clmul
+	}
+	if c&(1<<23) != 0 {
+		rval |= popcnt
+	}
+	if c&(1<<30) != 0 {
+		rval |= rdrand
+	}
+	if c&(1<<29) != 0 {
+		rval |= f16c
+	}
+	if c&(1<<13) != 0 {
+		rval |= cx16
+	}
+	if vend == intel && (d&(1<<28)) != 0 && mfi >= 4 {
+		if threadsPerCore() > 1 {
+			rval |= htt
+		}
+	}
+
+	// Check XGETBV, OXSAVE and AVX bits
+	if c&(1<<26) != 0 && c&(1<<27) != 0 && c&(1<<28) != 0 {
+		// Check for OS support
+		eax, _ := xgetbv(0)
+		if (eax & 0x6) == 0x6 {
+			rval |= avx
+			if (c & 0x00001000) != 0 {
+				rval |= fma3
+			}
+		}
+	}
+
+	// Check AVX2, AVX2 requires OS support, but BMI1/2 don't.
+	if mfi >= 7 {
+		_, ebx, ecx, _ := cpuidex(7, 0)
+		if (rval&avx) != 0 && (ebx&0x00000020) != 0 {
+			rval |= avx2
+		}
+		if (ebx & 0x00000008) != 0 {
+			rval |= bmi1
+			if (ebx & 0x00000100) != 0 {
+				rval |= bmi2
+			}
+		}
+		if ebx&(1<<4) != 0 {
+			rval |= hle
+		}
+		if ebx&(1<<9) != 0 {
+			rval |= erms
+		}
+		if ebx&(1<<11) != 0 {
+			rval |= rtm
+		}
+		if ebx&(1<<14) != 0 {
+			rval |= mpx
+		}
+		if ebx&(1<<18) != 0 {
+			rval |= rdseed
+		}
+		if ebx&(1<<19) != 0 {
+			rval |= adx
+		}
+		if ebx&(1<<29) != 0 {
+			rval |= sha
+		}
+
+		// Only detect AVX-512 features if XGETBV is supported
+		if c&((1<<26)|(1<<27)) == (1<<26)|(1<<27) {
+			// Check for OS support
+			eax, _ := xgetbv(0)
+
+			// Verify that XCR0[7:5] = ‘111b’ (OPMASK state, upper 256-bit of ZMM0-ZMM15 and
+			// ZMM16-ZMM31 state are enabled by OS)
+			/// and that XCR0[2:1] = ‘11b’ (XMM state and YMM state are enabled by OS).
+			if (eax>>5)&7 == 7 && (eax>>1)&3 == 3 {
+				if ebx&(1<<16) != 0 {
+					rval |= avx512f
+				}
+				if ebx&(1<<17) != 0 {
+					rval |= avx512dq
+				}
+				if ebx&(1<<21) != 0 {
+					rval |= avx512ifma
+				}
+				if ebx&(1<<26) != 0 {
+					rval |= avx512pf
+				}
+				if ebx&(1<<27) != 0 {
+					rval |= avx512er
+				}
+				if ebx&(1<<28) != 0 {
+					rval |= avx512cd
+				}
+				if ebx&(1<<30) != 0 {
+					rval |= avx512bw
+				}
+				if ebx&(1<<31) != 0 {
+					rval |= avx512vl
+				}
+				// ecx
+				if ecx&(1<<1) != 0 {
+					rval |= avx512vbmi
+				}
+			}
+		}
+	}
+
+	if maxExtendedFunction() >= 0x80000001 {
+		_, _, c, d := cpuid(0x80000001)
+		if (c & (1 << 5)) != 0 {
+			rval |= lzcnt
+			rval |= popcnt
+		}
+		if (d & (1 << 31)) != 0 {
+			rval |= amd3dnow
+		}
+		if (d & (1 << 30)) != 0 {
+			rval |= amd3dnowext
+		}
+		if (d & (1 << 23)) != 0 {
+			rval |= mmx
+		}
+		if (d & (1 << 22)) != 0 {
+			rval |= mmxext
+		}
+		if (c & (1 << 6)) != 0 {
+			rval |= sse4a
+		}
+		if d&(1<<20) != 0 {
+			rval |= nx
+		}
+		if d&(1<<27) != 0 {
+			rval |= rdtscp
+		}
+
+		/* Allow for selectively disabling SSE2 functions on AMD processors
+		   with SSE2 support but not SSE4a. This includes Athlon64, some
+		   Opteron, and some Sempron processors. MMX, SSE, or 3DNow! are faster
+		   than SSE2 often enough to utilize this special-case flag.
+		   AV_CPU_FLAG_SSE2 and AV_CPU_FLAG_SSE2SLOW are both set in this case
+		   so that SSE2 is used unless explicitly disabled by checking
+		   AV_CPU_FLAG_SSE2SLOW. */
+		if vendorID() != intel &&
+			rval&sse2 != 0 && (c&0x00000040) == 0 {
+			rval |= sse2slow
+		}
+
+		/* XOP and FMA4 use the AVX instruction coding scheme, so they can't be
+		 * used unless the OS has AVX support. */
+		if (rval & avx) != 0 {
+			if (c & 0x00000800) != 0 {
+				rval |= xop
+			}
+			if (c & 0x00010000) != 0 {
+				rval |= fma4
+			}
+		}
+
+		if vendorID() == intel {
+			family, model := familyModel()
+			if family == 6 && (model == 9 || model == 13 || model == 14) {
+				/* 6/9 (pentium-m "banias"), 6/13 (pentium-m "dothan"), and
+				 * 6/14 (core1 "yonah") theoretically support sse2, but it's
+				 * usually slower than mmx. */
+				if (rval & sse2) != 0 {
+					rval |= sse2slow
+				}
+				if (rval & sse3) != 0 {
+					rval |= sse3slow
+				}
+			}
+			/* The Atom processor has SSSE3 support, which is useful in many cases,
+			 * but sometimes the SSSE3 version is slower than the SSE2 equivalent
+			 * on the Atom, but is generally faster on other processors supporting
+			 * SSSE3. This flag allows for selectively disabling certain SSSE3
+			 * functions on the Atom. */
+			if family == 6 && model == 28 {
+				rval |= atom
+			}
+		}
+	}
+	return flags(rval)
+}
+
+func valAsString(values ...uint32) []byte {
+	r := make([]byte, 4*len(values))
+	for i, v := range values {
+		dst := r[i*4:]
+		dst[0] = byte(v & 0xff)
+		dst[1] = byte((v >> 8) & 0xff)
+		dst[2] = byte((v >> 16) & 0xff)
+		dst[3] = byte((v >> 24) & 0xff)
+		switch {
+		case dst[0] == 0:
+			return r[:i*4]
+		case dst[1] == 0:
+			return r[:i*4+1]
+		case dst[2] == 0:
+			return r[:i*4+2]
+		case dst[3] == 0:
+			return r[:i*4+3]
+		}
+	}
+	return r
+}

vendor/github.com/klauspost/cpuid/private/cpuid_386.s

@@ -0,0 +1,42 @@
+// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file.
+
+// +build 386,!gccgo
+
+// func asmCpuid(op uint32) (eax, ebx, ecx, edx uint32)
+TEXT ·asmCpuid(SB), 7, $0
+	XORL CX, CX
+	MOVL op+0(FP), AX
+	CPUID
+	MOVL AX, eax+4(FP)
+	MOVL BX, ebx+8(FP)
+	MOVL CX, ecx+12(FP)
+	MOVL DX, edx+16(FP)
+	RET
+
+// func asmCpuidex(op, op2 uint32) (eax, ebx, ecx, edx uint32)
+TEXT ·asmCpuidex(SB), 7, $0
+	MOVL op+0(FP), AX
+	MOVL op2+4(FP), CX
+	CPUID
+	MOVL AX, eax+8(FP)
+	MOVL BX, ebx+12(FP)
+	MOVL CX, ecx+16(FP)
+	MOVL DX, edx+20(FP)
+	RET
+
+// func xgetbv(index uint32) (eax, edx uint32)
+TEXT ·asmXgetbv(SB), 7, $0
+	MOVL index+0(FP), CX
+	BYTE $0x0f; BYTE $0x01; BYTE $0xd0 // XGETBV
+	MOVL AX, eax+4(FP)
+	MOVL DX, edx+8(FP)
+	RET
+
+// func asmRdtscpAsm() (eax, ebx, ecx, edx uint32)
+TEXT ·asmRdtscpAsm(SB), 7, $0
+	BYTE $0x0F; BYTE $0x01; BYTE $0xF9 // RDTSCP
+	MOVL AX, eax+0(FP)
+	MOVL BX, ebx+4(FP)
+	MOVL CX, ecx+8(FP)
+	MOVL DX, edx+12(FP)
+	RET

vendor/github.com/klauspost/cpuid/private/cpuid_amd64.s

@@ -0,0 +1,42 @@
+// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file.
+
+//+build amd64,!gccgo
+
+// func asmCpuid(op uint32) (eax, ebx, ecx, edx uint32)
+TEXT ·asmCpuid(SB), 7, $0
+	XORQ CX, CX
+	MOVL op+0(FP), AX
+	CPUID
+	MOVL AX, eax+8(FP)
+	MOVL BX, ebx+12(FP)
+	MOVL CX, ecx+16(FP)
+	MOVL DX, edx+20(FP)
+	RET
+
+// func asmCpuidex(op, op2 uint32) (eax, ebx, ecx, edx uint32)
+TEXT ·asmCpuidex(SB), 7, $0
+	MOVL op+0(FP), AX
+	MOVL op2+4(FP), CX
+	CPUID
+	MOVL AX, eax+8(FP)
+	MOVL BX, ebx+12(FP)
+	MOVL CX, ecx+16(FP)
+	MOVL DX, edx+20(FP)
+	RET
+
+// func asmXgetbv(index uint32) (eax, edx uint32)
+TEXT ·asmXgetbv(SB), 7, $0
+	MOVL index+0(FP), CX
+	BYTE $0x0f; BYTE $0x01; BYTE $0xd0 // XGETBV
+	MOVL AX, eax+8(FP)
+	MOVL DX, edx+12(FP)
+	RET
+
+// func asmRdtscpAsm() (eax, ebx, ecx, edx uint32)
+TEXT ·asmRdtscpAsm(SB), 7, $0
+	BYTE $0x0F; BYTE $0x01; BYTE $0xF9 // RDTSCP
+	MOVL AX, eax+0(FP)
+	MOVL BX, ebx+4(FP)
+	MOVL CX, ecx+8(FP)
+	MOVL DX, edx+12(FP)
+	RET

vendor/github.com/klauspost/cpuid/private/cpuid_detect_intel.go

@@ -0,0 +1,17 @@
+// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file.
+
+// +build 386,!gccgo amd64,!gccgo
+
+package cpuid
+
+func asmCpuid(op uint32) (eax, ebx, ecx, edx uint32)
+func asmCpuidex(op, op2 uint32) (eax, ebx, ecx, edx uint32)
+func asmXgetbv(index uint32) (eax, edx uint32)
+func asmRdtscpAsm() (eax, ebx, ecx, edx uint32)
+
+func initCPU() {
+	cpuid = asmCpuid
+	cpuidex = asmCpuidex
+	xgetbv = asmXgetbv
+	rdtscpAsm = asmRdtscpAsm
+}

vendor/github.com/klauspost/cpuid/private/cpuid_detect_ref.go

@@ -0,0 +1,23 @@
+// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file.
+
+// +build !amd64,!386 gccgo
+
+package cpuid
+
+func initCPU() {
+	cpuid = func(op uint32) (eax, ebx, ecx, edx uint32) {
+		return 0, 0, 0, 0
+	}
+
+	cpuidex = func(op, op2 uint32) (eax, ebx, ecx, edx uint32) {
+		return 0, 0, 0, 0
+	}
+
+	xgetbv = func(index uint32) (eax, edx uint32) {
+		return 0, 0
+	}
+
+	rdtscpAsm = func() (eax, ebx, ecx, edx uint32) {
+		return 0, 0, 0, 0
+	}
+}

vendor/github.com/klauspost/cpuid/private/cpuid_test.go

@@ -0,0 +1,719 @@
+// Generated, DO NOT EDIT,
+// but copy it to your own project and rename the package.
+// See more at http://github.com/klauspost/cpuid
+
+package cpuid
+
+import (
+	"fmt"
+	"testing"
+)
+
+// There is no real way to test a CPU identifier, since results will
+// obviously differ on each machine.
+func TestCPUID(t *testing.T) {
+	n := maxFunctionID()
+	t.Logf("Max Function:0x%x\n", n)
+	n = maxExtendedFunction()
+	t.Logf("Max Extended Function:0x%x\n", n)
+	t.Log("Name:", cpu.brandname)
+	t.Log("PhysicalCores:", cpu.physicalcores)
+	t.Log("ThreadsPerCore:", cpu.threadspercore)
+	t.Log("LogicalCores:", cpu.logicalcores)
+	t.Log("Family", cpu.family, "Model:", cpu.model)
+	t.Log("Features:", cpu.features)
+	t.Log("Cacheline bytes:", cpu.cacheline)
+	t.Log("L1 Instruction Cache:", cpu.cache.l1i, "bytes")
+	t.Log("L1 Data Cache:", cpu.cache.l1d, "bytes")
+	t.Log("L2 Cache:", cpu.cache.l2, "bytes")
+	t.Log("L3 Cache:", cpu.cache.l3, "bytes")
+
+	if cpu.sse2() {
+		t.Log("We have SSE2")
+	}
+}
+
+func TestDumpCPUID(t *testing.T) {
+	n := int(maxFunctionID())
+	for i := 0; i <= n; i++ {
+		a, b, c, d := cpuidex(uint32(i), 0)
+		t.Logf("CPUID %08x: %08x-%08x-%08x-%08x", i, a, b, c, d)
+		ex := uint32(1)
+		for {
+			a2, b2, c2, d2 := cpuidex(uint32(i), ex)
+			if a2 == a && b2 == b && d2 == d || ex > 50 || a2 == 0 {
+				break
+			}
+			t.Logf("CPUID %08x: %08x-%08x-%08x-%08x", i, a2, b2, c2, d2)
+			a, b, c, d = a2, b2, c2, d2
+			ex++
+		}
+	}
+	n2 := maxExtendedFunction()
+	for i := uint32(0x80000000); i <= n2; i++ {
+		a, b, c, d := cpuid(i)
+		t.Logf("CPUID %08x: %08x-%08x-%08x-%08x", i, a, b, c, d)
+	}
+}
+
+func example() {
+	// Print basic CPU information:
+	fmt.Println("Name:", cpu.brandname)
+	fmt.Println("PhysicalCores:", cpu.physicalcores)
+	fmt.Println("ThreadsPerCore:", cpu.threadspercore)
+	fmt.Println("LogicalCores:", cpu.logicalcores)
+	fmt.Println("Family", cpu.family, "Model:", cpu.model)
+	fmt.Println("Features:", cpu.features)
+	fmt.Println("Cacheline bytes:", cpu.cacheline)
+
+	// Test if we have a specific feature:
+	if cpu.sse() {
+		fmt.Println("We have Streaming SIMD Extensions")
+	}
+}
+
+func TestBrandNameZero(t *testing.T) {
+	if len(cpu.brandname) > 0 {
+		// Cut out last byte
+		last := []byte(cpu.brandname[len(cpu.brandname)-1:])
+		if last[0] == 0 {
+			t.Fatal("last byte was zero")
+		} else if last[0] == 32 {
+			t.Fatal("whitespace wasn't trimmed")
+		}
+	}
+}
+
+// Generated here: http://play.golang.org/p/mko-0tFt0Q
+
+// TestCmov tests Cmov() function
+func TestCmov(t *testing.T) {
+	got := cpu.cmov()
+	expected := cpu.features&cmov == cmov
+	if got != expected {
+		t.Fatalf("Cmov: expected %v, got %v", expected, got)
+	}
+	t.Log("CMOV Support:", got)
+}
+
+// TestAmd3dnow tests Amd3dnow() function
+func TestAmd3dnow(t *testing.T) {
+	got := cpu.amd3dnow()
+	expected := cpu.features&amd3dnow == amd3dnow
+	if got != expected {
+		t.Fatalf("Amd3dnow: expected %v, got %v", expected, got)
+	}
+	t.Log("AMD3DNOW Support:", got)
+}
+
+// TestAmd3dnowExt tests Amd3dnowExt() function
+func TestAmd3dnowExt(t *testing.T) {
+	got := cpu.amd3dnowext()
+	expected := cpu.features&amd3dnowext == amd3dnowext
+	if got != expected {
+		t.Fatalf("Amd3dnowExt: expected %v, got %v", expected, got)
+	}
+	t.Log("AMD3DNOWEXT Support:", got)
+}
+
+// TestMMX tests MMX() function
+func TestMMX(t *testing.T) {
+	got := cpu.mmx()
+	expected := cpu.features&mmx == mmx
+	if got != expected {
+		t.Fatalf("MMX: expected %v, got %v", expected, got)
+	}
+	t.Log("MMX Support:", got)
+}
+
+// TestMMXext tests MMXext() function
+func TestMMXext(t *testing.T) {
+	got := cpu.mmxext()
+	expected := cpu.features&mmxext == mmxext
+	if got != expected {
+		t.Fatalf("MMXExt: expected %v, got %v", expected, got)
+	}
+	t.Log("MMXEXT Support:", got)
+}
+
+// TestSSE tests SSE() function
+func TestSSE(t *testing.T) {
+	got := cpu.sse()
+	expected := cpu.features&sse == sse
+	if got != expected {
+		t.Fatalf("SSE: expected %v, got %v", expected, got)
+	}
+	t.Log("SSE Support:", got)
+}
+
+// TestSSE2 tests SSE2() function
+func TestSSE2(t *testing.T) {
+	got := cpu.sse2()
+	expected := cpu.features&sse2 == sse2
+	if got != expected {
+		t.Fatalf("SSE2: expected %v, got %v", expected, got)
+	}
+	t.Log("SSE2 Support:", got)
+}
+
+// TestSSE3 tests SSE3() function
+func TestSSE3(t *testing.T) {
+	got := cpu.sse3()
+	expected := cpu.features&sse3 == sse3
+	if got != expected {
+		t.Fatalf("SSE3: expected %v, got %v", expected, got)
+	}
+	t.Log("SSE3 Support:", got)
+}
+
+// TestSSSE3 tests SSSE3() function
+func TestSSSE3(t *testing.T) {
+	got := cpu.ssse3()
+	expected := cpu.features&ssse3 == ssse3
+	if got != expected {
+		t.Fatalf("SSSE3: expected %v, got %v", expected, got)
+	}
+	t.Log("SSSE3 Support:", got)
+}
+
+// TestSSE4 tests SSE4() function
+func TestSSE4(t *testing.T) {
+	got := cpu.sse4()
+	expected := cpu.features&sse4 == sse4
+	if got != expected {
+		t.Fatalf("SSE4: expected %v, got %v", expected, got)
+	}
+	t.Log("SSE4 Support:", got)
+}
+
+// TestSSE42 tests SSE42() function
+func TestSSE42(t *testing.T) {
+	got := cpu.sse42()
+	expected := cpu.features&sse42 == sse42
+	if got != expected {
+		t.Fatalf("SSE42: expected %v, got %v", expected, got)
+	}
+	t.Log("SSE42 Support:", got)
+}
+
+// TestAVX tests AVX() function
+func TestAVX(t *testing.T) {
+	got := cpu.avx()
+	expected := cpu.features&avx == avx
+	if got != expected {
+		t.Fatalf("AVX: expected %v, got %v", expected, got)
+	}
+	t.Log("AVX Support:", got)
+}
+
+// TestAVX2 tests AVX2() function
+func TestAVX2(t *testing.T) {
+	got := cpu.avx2()
+	expected := cpu.features&avx2 == avx2
+	if got != expected {
+		t.Fatalf("AVX2: expected %v, got %v", expected, got)
+	}
+	t.Log("AVX2 Support:", got)
+}
+
+// TestFMA3 tests FMA3() function
+func TestFMA3(t *testing.T) {
+	got := cpu.fma3()
+	expected := cpu.features&fma3 == fma3
+	if got != expected {
+		t.Fatalf("FMA3: expected %v, got %v", expected, got)
+	}
+	t.Log("FMA3 Support:", got)
+}
+
+// TestFMA4 tests FMA4() function
+func TestFMA4(t *testing.T) {
+	got := cpu.fma4()
+	expected := cpu.features&fma4 == fma4
+	if got != expected {
+		t.Fatalf("FMA4: expected %v, got %v", expected, got)
+	}
+	t.Log("FMA4 Support:", got)
+}
+
+// TestXOP tests XOP() function
+func TestXOP(t *testing.T) {
+	got := cpu.xop()
+	expected := cpu.features&xop == xop
+	if got != expected {
+		t.Fatalf("XOP: expected %v, got %v", expected, got)
+	}
+	t.Log("XOP Support:", got)
+}
+
+// TestF16C tests F16C() function
+func TestF16C(t *testing.T) {
+	got := cpu.f16c()
+	expected := cpu.features&f16c == f16c
+	if got != expected {
+		t.Fatalf("F16C: expected %v, got %v", expected, got)
+	}
+	t.Log("F16C Support:", got)
+}
+
+// TestCX16 tests CX16() function
+func TestCX16(t *testing.T) {
+	got := cpu.cx16()
+	expected := cpu.features&cx16 == cx16
+	if got != expected {
+		t.Fatalf("CX16: expected %v, got %v", expected, got)
+	}
+	t.Log("CX16 Support:", got)
+}
+
+// TestBMI1 tests BMI1() function
+func TestBMI1(t *testing.T) {
+	got := cpu.bmi1()
+	expected := cpu.features&bmi1 == bmi1
+	if got != expected {
+		t.Fatalf("BMI1: expected %v, got %v", expected, got)
+	}
+	t.Log("BMI1 Support:", got)
+}
+
+// TestBMI2 tests BMI2() function
+func TestBMI2(t *testing.T) {
+	got := cpu.bmi2()
+	expected := cpu.features&bmi2 == bmi2
+	if got != expected {
+		t.Fatalf("BMI2: expected %v, got %v", expected, got)
+	}
+	t.Log("BMI2 Support:", got)
+}
+
+// TestTBM tests TBM() function
+func TestTBM(t *testing.T) {
+	got := cpu.tbm()
+	expected := cpu.features&tbm == tbm
+	if got != expected {
+		t.Fatalf("TBM: expected %v, got %v", expected, got)
+	}
+	t.Log("TBM Support:", got)
+}
+
+// TestLzcnt tests Lzcnt() function
+func TestLzcnt(t *testing.T) {
+	got := cpu.lzcnt()
+	expected := cpu.features&lzcnt == lzcnt
+	if got != expected {
+		t.Fatalf("Lzcnt: expected %v, got %v", expected, got)
+	}
+	t.Log("LZCNT Support:", got)
+}
+
+// TestLzcnt tests Lzcnt() function
+func TestPopcnt(t *testing.T) {
+	got := cpu.popcnt()
+	expected := cpu.features&popcnt == popcnt
+	if got != expected {
+		t.Fatalf("Popcnt: expected %v, got %v", expected, got)
+	}
+	t.Log("POPCNT Support:", got)
+}
+
+// TestAesNi tests AesNi() function
+func TestAesNi(t *testing.T) {
+	got := cpu.aesni()
+	expected := cpu.features&aesni == aesni
+	if got != expected {
+		t.Fatalf("AesNi: expected %v, got %v", expected, got)
+	}
+	t.Log("AESNI Support:", got)
+}
+
+// TestHTT tests HTT() function
+func TestHTT(t *testing.T) {
+	got := cpu.htt()
+	expected := cpu.features&htt == htt
+	if got != expected {
+		t.Fatalf("HTT: expected %v, got %v", expected, got)
+	}
+	t.Log("HTT Support:", got)
+}
+
+// TestClmul tests Clmul() function
+func TestClmul(t *testing.T) {
+	got := cpu.clmul()
+	expected := cpu.features&clmul == clmul
+	if got != expected {
+		t.Fatalf("Clmul: expected %v, got %v", expected, got)
+	}
+	t.Log("CLMUL Support:", got)
+}
+
+// TestSSE2Slow tests SSE2Slow() function
+func TestSSE2Slow(t *testing.T) {
+	got := cpu.sse2slow()
+	expected := cpu.features&sse2slow == sse2slow
+	if got != expected {
+		t.Fatalf("SSE2Slow: expected %v, got %v", expected, got)
+	}
+	t.Log("SSE2SLOW Support:", got)
+}
+
+// TestSSE3Slow tests SSE3slow() function
+func TestSSE3Slow(t *testing.T) {
+	got := cpu.sse3slow()
+	expected := cpu.features&sse3slow == sse3slow
+	if got != expected {
+		t.Fatalf("SSE3slow: expected %v, got %v", expected, got)
+	}
+	t.Log("SSE3SLOW Support:", got)
+}
+
+// TestAtom tests Atom() function
+func TestAtom(t *testing.T) {
+	got := cpu.atom()
+	expected := cpu.features&atom == atom
+	if got != expected {
+		t.Fatalf("Atom: expected %v, got %v", expected, got)
+	}
+	t.Log("ATOM Support:", got)
+}
+
+// TestNX tests NX() function (NX (No-Execute) bit)
+func TestNX(t *testing.T) {
+	got := cpu.nx()
+	expected := cpu.features&nx == nx
+	if got != expected {
+		t.Fatalf("NX: expected %v, got %v", expected, got)
+	}
+	t.Log("NX Support:", got)
+}
+
+// TestSSE4A tests SSE4A() function (AMD Barcelona microarchitecture SSE4a instructions)
+func TestSSE4A(t *testing.T) {
+	got := cpu.sse4a()
+	expected := cpu.features&sse4a == sse4a
+	if got != expected {
+		t.Fatalf("SSE4A: expected %v, got %v", expected, got)
+	}
+	t.Log("SSE4A Support:", got)
+}
+
+// TestHLE tests HLE() function (Hardware Lock Elision)
+func TestHLE(t *testing.T) {
+	got := cpu.hle()
+	expected := cpu.features&hle == hle
+	if got != expected {
+		t.Fatalf("HLE: expected %v, got %v", expected, got)
+	}
+	t.Log("HLE Support:", got)
+}
+
+// TestRTM tests RTM() function (Restricted Transactional Memory)
+func TestRTM(t *testing.T) {
+	got := cpu.rtm()
+	expected := cpu.features&rtm == rtm
+	if got != expected {
+		t.Fatalf("RTM: expected %v, got %v", expected, got)
+	}
+	t.Log("RTM Support:", got)
+}
+
+// TestRdrand tests RDRAND() function (RDRAND instruction is available)
+func TestRdrand(t *testing.T) {
+	got := cpu.rdrand()
+	expected := cpu.features&rdrand == rdrand
+	if got != expected {
+		t.Fatalf("Rdrand: expected %v, got %v", expected, got)
+	}
+	t.Log("Rdrand Support:", got)
+}
+
+// TestRdseed tests RDSEED() function (RDSEED instruction is available)
+func TestRdseed(t *testing.T) {
+	got := cpu.rdseed()
+	expected := cpu.features&rdseed == rdseed
+	if got != expected {
+		t.Fatalf("Rdseed: expected %v, got %v", expected, got)
+	}
+	t.Log("Rdseed Support:", got)
+}
+
+// TestADX tests ADX() function (Intel ADX (Multi-Precision Add-Carry Instruction Extensions))
+func TestADX(t *testing.T) {
+	got := cpu.adx()
+	expected := cpu.features&adx == adx
+	if got != expected {
+		t.Fatalf("ADX: expected %v, got %v", expected, got)
+	}
+	t.Log("ADX Support:", got)
+}
+
+// TestSHA tests SHA() function (Intel SHA Extensions)
+func TestSHA(t *testing.T) {
+	got := cpu.sha()
+	expected := cpu.features&sha == sha
+	if got != expected {
+		t.Fatalf("SHA: expected %v, got %v", expected, got)
+	}
+	t.Log("SHA Support:", got)
+}
+
+// TestAVX512F tests AVX512F() function (AVX-512 Foundation)
+func TestAVX512F(t *testing.T) {
+	got := cpu.avx512f()
+	expected := cpu.features&avx512f == avx512f
+	if got != expected {
+		t.Fatalf("AVX512F: expected %v, got %v", expected, got)
+	}
+	t.Log("AVX512F Support:", got)
+}
+
+// TestAVX512DQ tests AVX512DQ() function (AVX-512 Doubleword and Quadword Instructions)
+func TestAVX512DQ(t *testing.T) {
+	got := cpu.avx512dq()
+	expected := cpu.features&avx512dq == avx512dq
+	if got != expected {
+		t.Fatalf("AVX512DQ: expected %v, got %v", expected, got)
+	}
+	t.Log("AVX512DQ Support:", got)
+}
+
+// TestAVX512IFMA tests AVX512IFMA() function (AVX-512 Integer Fused Multiply-Add Instructions)
+func TestAVX512IFMA(t *testing.T) {
+	got := cpu.avx512ifma()
+	expected := cpu.features&avx512ifma == avx512ifma
+	if got != expected {
+		t.Fatalf("AVX512IFMA: expected %v, got %v", expected, got)
+	}
+	t.Log("AVX512IFMA Support:", got)
+}
+
+// TestAVX512PF tests AVX512PF() function (AVX-512 Prefetch Instructions)
+func TestAVX512PF(t *testing.T) {
+	got := cpu.avx512pf()
+	expected := cpu.features&avx512pf == avx512pf
+	if got != expected {
+		t.Fatalf("AVX512PF: expected %v, got %v", expected, got)
+	}
+	t.Log("AVX512PF Support:", got)
+}
+
+// TestAVX512ER tests AVX512ER() function (AVX-512 Exponential and Reciprocal Instructions)
+func TestAVX512ER(t *testing.T) {
+	got := cpu.avx512er()
+	expected := cpu.features&avx512er == avx512er
+	if got != expected {
+		t.Fatalf("AVX512ER: expected %v, got %v", expected, got)
+	}
+	t.Log("AVX512ER Support:", got)
+}
+
+// TestAVX512CD tests AVX512CD() function (AVX-512 Conflict Detection Instructions)
+func TestAVX512CD(t *testing.T) {
+	got := cpu.avx512cd()
+	expected := cpu.features&avx512cd == avx512cd
+	if got != expected {
+		t.Fatalf("AVX512CD: expected %v, got %v", expected, got)
+	}
+	t.Log("AVX512CD Support:", got)
+}
+
+// TestAVX512BW tests AVX512BW() function (AVX-512 Byte and Word Instructions)
+func TestAVX512BW(t *testing.T) {
+	got := cpu.avx512bw()
+	expected := cpu.features&avx512bw == avx512bw
+	if got != expected {
+		t.Fatalf("AVX512BW: expected %v, got %v", expected, got)
+	}
+	t.Log("AVX512BW Support:", got)
+}
+
+// TestAVX512VL tests AVX512VL() function (AVX-512 Vector Length Extensions)
+func TestAVX512VL(t *testing.T) {
+	got := cpu.avx512vl()
+	expected := cpu.features&avx512vl == avx512vl
+	if got != expected {
+		t.Fatalf("AVX512VL: expected %v, got %v", expected, got)
+	}
+	t.Log("AVX512VL Support:", got)
+}
+
+// TestAVX512VL tests AVX512VBMI() function (AVX-512 Vector Bit Manipulation Instructions)
+func TestAVX512VBMI(t *testing.T) {
+	got := cpu.avx512vbmi()
+	expected := cpu.features&avx512vbmi == avx512vbmi
+	if got != expected {
+		t.Fatalf("AVX512VBMI: expected %v, got %v", expected, got)
+	}
+	t.Log("AVX512VBMI Support:", got)
+}
+
+// TestMPX tests MPX() function (Intel MPX (Memory Protection Extensions))
+func TestMPX(t *testing.T) {
+	got := cpu.mpx()
+	expected := cpu.features&mpx == mpx
+	if got != expected {
+		t.Fatalf("MPX: expected %v, got %v", expected, got)
+	}
+	t.Log("MPX Support:", got)
+}
+
+// TestERMS tests ERMS() function (Enhanced REP MOVSB/STOSB)
+func TestERMS(t *testing.T) {
+	got := cpu.erms()
+	expected := cpu.features&erms == erms
+	if got != expected {
+		t.Fatalf("ERMS: expected %v, got %v", expected, got)
+	}
+	t.Log("ERMS Support:", got)
+}
+
+// TestVendor writes the detected vendor. Will be 0 if unknown
+func TestVendor(t *testing.T) {
+	t.Log("Vendor ID:", cpu.vendorid)
+}
+
+// Intel returns true if vendor is recognized as Intel
+func TestIntel(t *testing.T) {
+	got := cpu.intel()
+	expected := cpu.vendorid == intel
+	if got != expected {
+		t.Fatalf("TestIntel: expected %v, got %v", expected, got)
+	}
+	t.Log("TestIntel:", got)
+}
+
+// AMD returns true if vendor is recognized as AMD
+func TestAMD(t *testing.T) {
+	got := cpu.amd()
+	expected := cpu.vendorid == amd
+	if got != expected {
+		t.Fatalf("TestAMD: expected %v, got %v", expected, got)
+	}
+	t.Log("TestAMD:", got)
+}
+
+// Transmeta returns true if vendor is recognized as Transmeta
+func TestTransmeta(t *testing.T) {
+	got := cpu.transmeta()
+	expected := cpu.vendorid == transmeta
+	if got != expected {
+		t.Fatalf("TestTransmeta: expected %v, got %v", expected, got)
+	}
+	t.Log("TestTransmeta:", got)
+}
+
+// NSC returns true if vendor is recognized as National Semiconductor
+func TestNSC(t *testing.T) {
+	got := cpu.nsc()
+	expected := cpu.vendorid == nsc
+	if got != expected {
+		t.Fatalf("TestNSC: expected %v, got %v", expected, got)
+	}
+	t.Log("TestNSC:", got)
+}
+
+// VIA returns true if vendor is recognized as VIA
+func TestVIA(t *testing.T) {
+	got := cpu.via()
+	expected := cpu.vendorid == via
+	if got != expected {
+		t.Fatalf("TestVIA: expected %v, got %v", expected, got)
+	}
+	t.Log("TestVIA:", got)
+}
+
+// Test VM function
+func TestVM(t *testing.T) {
+	t.Log("Vendor ID:", cpu.vm())
+}
+
+// Test RTCounter function
+func TestRtCounter(t *testing.T) {
+	a := cpu.rtcounter()
+	b := cpu.rtcounter()
+	t.Log("CPU Counter:", a, b, b-a)
+}
+
+// Prints the value of Ia32TscAux()
+func TestIa32TscAux(t *testing.T) {
+	ecx := cpu.ia32tscaux()
+	t.Logf("Ia32TscAux:0x%x\n", ecx)
+	if ecx != 0 {
+		chip := (ecx & 0xFFF000) >> 12
+		core := ecx & 0xFFF
+		t.Log("Likely chip, core:", chip, core)
+	}
+}
+
+func TestThreadsPerCoreNZ(t *testing.T) {
+	if cpu.threadspercore == 0 {
+		t.Fatal("threads per core is zero")
+	}
+}
+
+// Prints the value of LogicalCPU()
+func TestLogicalCPU(t *testing.T) {
+	t.Log("Currently executing on cpu:", cpu.logicalcpu())
+}
+
+func TestMaxFunction(t *testing.T) {
+	expect := maxFunctionID()
+	if cpu.maxFunc != expect {
+		t.Fatal("Max function does not match, expected", expect, "but got", cpu.maxFunc)
+	}
+	expect = maxExtendedFunction()
+	if cpu.maxExFunc != expect {
+		t.Fatal("Max Extended function does not match, expected", expect, "but got", cpu.maxFunc)
+	}
+}
+
+// This example will calculate the chip/core number on Linux
+// Linux encodes numa id (<<12) and core id (8bit) into TSC_AUX.
+func examplecpuinfo_ia32tscaux(t *testing.T) {
+	ecx := cpu.ia32tscaux()
+	if ecx == 0 {
+		fmt.Println("Unknown CPU ID")
+		return
+	}
+	chip := (ecx & 0xFFF000) >> 12
+	core := ecx & 0xFFF
+	fmt.Println("Chip, Core:", chip, core)
+}
+
+/*
+func TestPhysical(t *testing.T) {
+	var test16 = "CPUID 00000000: 0000000d-756e6547-6c65746e-49656e69 \nCPUID 00000001: 000206d7-03200800-1fbee3ff-bfebfbff   \nCPUID 00000002: 76035a01-00f0b2ff-00000000-00ca0000   \nCPUID 00000003: 00000000-00000000-00000000-00000000   \nCPUID 00000004: 3c004121-01c0003f-0000003f-00000000   \nCPUID 00000004: 3c004122-01c0003f-0000003f-00000000   \nCPUID 00000004: 3c004143-01c0003f-000001ff-00000000   \nCPUID 00000004: 3c07c163-04c0003f-00003fff-00000006   \nCPUID 00000005: 00000040-00000040-00000003-00021120   \nCPUID 00000006: 00000075-00000002-00000009-00000000   \nCPUID 00000007: 00000000-00000000-00000000-00000000   \nCPUID 00000008: 00000000-00000000-00000000-00000000   \nCPUID 00000009: 00000001-00000000-00000000-00000000   \nCPUID 0000000a: 07300403-00000000-00000000-00000603   \nCPUID 0000000b: 00000000-00000000-00000003-00000003   \nCPUID 0000000b: 00000005-00000010-00000201-00000003   \nCPUID 0000000c: 00000000-00000000-00000000-00000000   \nCPUID 0000000d: 00000007-00000340-00000340-00000000   \nCPUID 0000000d: 00000001-00000000-00000000-00000000   \nCPUID 0000000d: 00000100-00000240-00000000-00000000   \nCPUID 80000000: 80000008-00000000-00000000-00000000   \nCPUID 80000001: 00000000-00000000-00000001-2c100800   \nCPUID 80000002: 20202020-49202020-6c65746e-20295228   \nCPUID 80000003: 6e6f6558-20295228-20555043-322d3545   \nCPUID 80000004: 20303636-20402030-30322e32-007a4847   \nCPUID 80000005: 00000000-00000000-00000000-00000000   \nCPUID 80000006: 00000000-00000000-01006040-00000000   \nCPUID 80000007: 00000000-00000000-00000000-00000100   \nCPUID 80000008: 0000302e-00000000-00000000-00000000"
+	restore := mockCPU([]byte(test16))
+	Detect()
+	t.Log("Name:", CPU.BrandName)
+	n := maxFunctionID()
+	t.Logf("Max Function:0x%x\n", n)
+	n = maxExtendedFunction()
+	t.Logf("Max Extended Function:0x%x\n", n)
+	t.Log("PhysicalCores:", CPU.PhysicalCores)
+	t.Log("ThreadsPerCore:", CPU.ThreadsPerCore)
+	t.Log("LogicalCores:", CPU.LogicalCores)
+	t.Log("Family", CPU.Family, "Model:", CPU.Model)
+	t.Log("Features:", CPU.Features)
+	t.Log("Cacheline bytes:", CPU.CacheLine)
+	t.Log("L1 Instruction Cache:", CPU.Cache.L1I, "bytes")
+	t.Log("L1 Data Cache:", CPU.Cache.L1D, "bytes")
+	t.Log("L2 Cache:", CPU.Cache.L2, "bytes")
+	t.Log("L3 Cache:", CPU.Cache.L3, "bytes")
+	if CPU.LogicalCores > 0 && CPU.PhysicalCores > 0 {
+		if CPU.LogicalCores != CPU.PhysicalCores*CPU.ThreadsPerCore {
+			t.Fatalf("Core count mismatch, LogicalCores (%d) != PhysicalCores (%d) * CPU.ThreadsPerCore (%d)",
+				CPU.LogicalCores, CPU.PhysicalCores, CPU.ThreadsPerCore)
+		}
+	}
+
+	if CPU.ThreadsPerCore > 1 && !CPU.HTT() {
+		t.Fatalf("Hyperthreading not detected")
+	}
+	if CPU.ThreadsPerCore == 1 && CPU.HTT() {
+		t.Fatalf("Hyperthreading detected, but only 1 Thread per core")
+	}
+	restore()
+	Detect()
+	TestCPUID(t)
+}
+*/